Till now we have seen regular sampling of signals. In Vera we have additional features to make this sampling of signals more powerful. In this page we will seeing some of these features.

The expect event asserts that a given signal has a given value at a given time. There are several forms of the expect primitive.

• Simple expect - @, == (!=)
• Full expect - @@, == (!=)
• Restricted - @@@, == (!=)

The simple expect checks that a given signal has a specific value at a given time. If the signal value does not match the expression when the check is made, a simulation error is generated. If a subfield within the signal is specified, all other bits in the signal are ignored and only those specified are checked against the expression.

Multiple expressions can be defined in the expect_list. If multiple expressions are defined (and separated by ",") the expect is satisfied if all of the conditions are satisfied at the time of the sample. Expressions can also be separated by the or keyword. In that case, the expect is satisfied if any of the conditions are satisfied at the time of the check.

Full expects check that a signal has a given value over the entire length of a given interval. Full expects behave in the same manner as simple expects with one exception. The signal value must match the expression over the entire course of the defined window. Multiple expressions can be checked using comma-separated lists. If all signals do not match during any part of the interval, the expect is not satisfied and a simulation error is generated.

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