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Sub-Cycle Delays
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Vera provides the delay() system task to block Vera while a specified amount of time elapses on the HDL side of the simulation. |
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Syntax |
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task delay(integer time); |
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- time : specifies the length of the delay. It is in the same timing units being used by the HDL.
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Example: Sub-Cycle Delays
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Simulation : Sub-Cycle Delays
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Copyright © 1998-2025 |
Deepak Kumar Tala - All rights reserved |
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Do you have any Comment? mail me at:deepak@asic-world.com
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