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Array of bins creation
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Systemverilog provides syntax to create array of bins in automatic way, but in explicity way for values. |
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Example : Array of bins creation
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1 module test();
2
3 logic [7:0] addr;
4 reg ce;
5
6 covergroup address_cov () @ (posedge ce);
7 ADDRESS : coverpoint addr {
8 // This should create 11 bins
9 bins low[] = {[0:10]};
10 // This should create 10 bins
11 bins med[] = {[11:20]};
12 }
13 endgroup
14
15 address_cov my_cov = new();
16
17 initial begin
18 ce <= 0;
19 addr <= 0;
20 $monitor("ce %b addr 8'h%x",ce,addr);
21 repeat (10) begin
22 addr = $random();
23 ce <= 1;
24 #10 ;
25 ce <= 0;
26 #10 ;
27 end
28 end
29
30 endmodule
You could download file array_bin.sv here
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Simulation : Array of bins creation
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ce 1 addr 8'h00
ce 0 addr 8'h00
ce 1 addr 8'h81
ce 0 addr 8'h81
ce 1 addr 8'h09
ce 0 addr 8'h09
ce 1 addr 8'h63
ce 0 addr 8'h63
ce 1 addr 8'h0d
ce 0 addr 8'h0d
ce 1 addr 8'h8d
ce 0 addr 8'h8d
ce 1 addr 8'h65
ce 0 addr 8'h65
ce 1 addr 8'h12
ce 0 addr 8'h12
ce 1 addr 8'h01
ce 0 addr 8'h01
ce 1 addr 8'h0d
ce 0 addr 8'h0d
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Report : Array of bins creation
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===========================================================
Group : test::address_cov
===========================================================
SCORE WEIGHT GOAL
23.81 1 100
-----------------------------------------------------------
Summary for Group test::address_cov
CATEGORY EXPECTED UNCOVERED COVERED PERCENT
Variables 21 16 5 23.81
Variables for Group test::address_cov
VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT
ADDRESS 21 16 5 23.81 100 1
-----------------------------------------------------------
Summary for Variable ADDRESS
CATEGORY EXPECTED UNCOVERED COVERED PERCENT
User Defined Bins 21 16 5 23.81
User Defined Bins for ADDRESS
Uncovered bins
NAME COUNT AT LEAST NUMBER
med_0b 0 1 1
med_0c 0 1 1
med_0e 0 1 1
med_0f 0 1 1
med_10 0 1 1
med_11 0 1 1
med_13 0 1 1
med_14 0 1 1
low_02 0 1 1
low_03 0 1 1
low_04 0 1 1
low_05 0 1 1
low_06 0 1 1
low_07 0 1 1
low_08 0 1 1
low_0a 0 1 1
Covered bins
NAME COUNT AT LEAST
med_0d 2 1
med_12 1 1
low_00 1 1
low_01 1 1
low_09 1 1
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Copyright © 1998-2014 |
Deepak Kumar Tala - All rights reserved |
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Do you have any Comment? mail me at:deepak@asic-world.com
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