A set of values or transitions associated with a coverage point can be marked as illegal by specifying them as illegal_bins. Hitting a illegal bin can cause simulator to terminate simulation.

Normally illegal bin syntax should be used on coverage points on variables inside DUT or on ports which are output of DUT. Having illegal bin syntax on testbench stimulus could prevent error injection.

  1 module test();
  2 
  3 logic [2:0] addr;
  4 reg ce;
  5 
  6 covergroup address_cov () @ (posedge ce);
  7   ADDRESS : coverpoint addr {
  8     ignore_bins ignore_tran = (0=>2=>1);
  9     ignore_bins ignore_vals = {0,1,2,3};
 10     illegal_bins ignore     = {5};
 11   }
 12 endgroup
 13 
 14 address_cov my_cov = new();
 15 
 16 initial begin
 17   ce   <= 0;
 18   $monitor("ce %b addr 8'h%x",ce,addr);
 19   repeat (10) begin
 20     ce <= 1;
 21     addr <= $urandom_range(0,7);
 22      #10 ;
 23     ce <= 0;
 24      #10 ;
 25   end
 26 end
 27 
 28 endmodule

 ce 1 addr 8'h6
 ce 0 addr 8'h6
 ce 1 addr 8'h4
 ce 0 addr 8'h4
 
 Error-[FCIBH] Illegal bin hit
 /code/systemverilog/illegal_bin.sv, 7
 test, "address_cov"
   VERIFICATION ERROR (FUNCTIONAL COVERAGE) : Illegal state bin ignore of 
   coverpoint ADDRESS in covergroup address_cov got hit with value 0x5
   Covergroup Instance: my_cov 
   Design hierarchy: test

 ===========================================================
 Group : test::address_cov
 ===========================================================
 SCORE  WEIGHT GOAL   
  66.67 1      100    
 -----------------------------------------------------------
 Summary for Group   test::address_cov
 
 CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
 Variables 3        1         2       66.67   
 
 Variables for Group  test::address_cov
 
 VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT 
 ADDRESS  3        1         2       66.67   100  1      
 -----------------------------------------------------------
 Summary for Variable ADDRESS
 
 CATEGORY                     EXPECTED UNCOVERED COVERED PERCENT 
 Automatically Generated Bins 3        1         2       66.67   
 
 Automatically Generated Bins for ADDRESS
 
 Uncovered bins
 
 NAME      COUNT AT LEAST NUMBER 
 [auto[7]] 0     1        1      
 
 Excluded/Illegal bins
 
 NAME                COUNT                   
 ignore_tran         0     Excluded 
 ignore_vals         0     Excluded 
 ignore              1     Excluded 
 [auto[0] - auto[3]] --    Excluded (4 bins) 
 [auto[5]]           0     Illegal  
 
 Covered bins
 
 NAME    COUNT AT LEAST  
 auto[4] 1     1        
 auto[6] 1     1        

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