This section is about frequent questions asked about Verilog Tools.

There are not many options; you could start with Icarus Verilog simulator, this is very actively developed. Currently synthesis support is being added. I hope someday this simulator will support all the Verilog constructs.

Verilator : Verilator is a compiled cycle-based simulator, which is free, but performs as fast as the commercial products.

There are very few commercial simulators which offer student versions.

• Silos from Simucad offers 350 lines in demo mode. Good enough for students projects.
• Finsim from Fintronic offers 350 Components for $100 as student version.

VCD - Value Change Dump format - is an ASCII file that contains the "Changes in Values of Signals". This is a STANDARD format and is compatible between different waveform viewers etc. Also most of the simulators can write out VCD files - both VHDL & Verilog, though in Verilog you could do it more easily (than in VHDL - where you have to go through your simulator's C-API) with the system tasks like $dumpvars.

There are the following free tools:

• Dinotrace : Freeware VCD viewer from Veritools
• GTKWave: Freeware VCD viewer, seems far better then other free VCD viewers.

The answer is not as simple as the question itself, let me just list the popular simulators:

• Modelsim : Good for debugging at unit level, but very slow for full chip level simulations. Good for mixed HDL simulation.
• VCS : Fastest simulator out there, but somehow I always had problems with their GUI debugger. Version 7.0 supports lots of good features.
• NCSIM : Very good simulator, most of the mixed HDL design are done today on this.
• Finsim : fast, but also light on pocket.
• Aldec : One more mixed HDL simulator, which seems to be picking up market.
• athdl : Athdl is a new player in simulator market, they seem to match speed of simulation with NCSIM.

• Cycle based Simulator :Cycle simulation is a technique (i.e. an algorithm) for digital circuit simulation. It does not simulate detailed circuit timing, but instead computes the steady state response of a circuit at each clock cycle. The user cannot see the glitch behavior of signals between clock cycles. Instead the user observes circuit signals once per clock cycle. Cycle based simulators work only with synchronous designs.
• Event based Simulator: Simulation based on events in logic means that whenever there is change in a input event, the output is evaluated. This makes the simulation very slow compared to Cycle based simulators. Verilog-XL is an event based simulator.

Consider the circuit below: if a cycle based simulator runs a simulation on the circuit below, then it will evaluate B, C, D and E only at each cycle. In the case of an event based simulator, B, C, D and E are evaluated not only at clock cycle, but also when any of the events at the input of gates and flip-flops occurs.

• Compiled Simulator : This kind of simulator converts the whole Verilog code into machine dependent code and then runs the simulation. Example : VCS generates the binary file, which can be run from the command prompt. Compiled simulators are very fast.
• Interpreted Simulator : This kind of simulator executes line by line, thus is very slow compared to a compiled simulator. Verilog-XL is one such simulator.

You can always check the FPGA vendors like Altera and Xilinx. These companies always give free version of their tools. This are not state of the art synthesis tools, but are good enough for new learners.

There are tons of editors out there. The most widely used editors are:

• vi or Gvim : Freeware, most engineers out there use this.
• Emacs : Most engineers use this too.
• Nedit : One more Unix based editor.
• Prism : Those who want to edit files in the Windows platform.
• HDL Turbo Writer : The best in its class, but expensive for an editor.

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Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com