Verilog Synthesis Tutorial

What is logic synthesis ?

	Life before HDL (Logic synthesis)
	Impact of HDL and Logic synthesis.
	What do we discuss here ?

Constructs Not Supported in Synthesis

Example of Non-Synthesizable Verilog construct.

	Example - Initial Statement
	Delays

Comparison to X and Z are always ignored

Constructs Supported in Synthesis

Operators and their Effect.

Logic Circuit Modeling

Combinational Circuit Modeling using assign

	Tri-state buffer
	Mux
	Simple Concatenation
	1 bit adder with carry
	Multiply by 2
	3 is to 8 decoder

Combinational Circuit Modeling using always

3 is to 8 decoder using always

Sequential Circuit Modeling

Simple Flip-Flop

Verilog Coding Style

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Deepak Kumar Tala - All rights reserved

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