Verification flow with VERA is same as with any other HVL's. Below figure shows the verification flow with VERA.

Verification flow starts with understanding specification of the chip/block under verification. Once the specification is understood, test cases document is prepared, which documents all the possible test cases. Once test case document is done to a level, where 70-80 percent functionality is covered, testbench architecture document is prepared. In the past, testbench architecture document is prepared first and test case document is prepared next. There is a draw back with this style, If test case document show a particular functionality to be verified and If testbench does not support as architecture document was prepared before test cases document. If we have test cases document to refer to, then writing architecture documented becomes much easier, as we know for sure what is expected from the testbench.

Identifying the test cases from the design specification is a simple task for simple cases. Normally any requirement in design specification becomes a test cases. Anything that specification mentions "Can do", "will have" becomes a test case. Corner test cases normally takes lot of thinking to identify.

Typical TestBench architecture looks as shown below. The main blocks in a testbench are base object, transaction generator, driver, monitor, checker/scoreboard.

The bock in red is DUT, and boxes in orange are testbench components. Coverage is a separate block, which gets events from input monitor and output monitor. This is same a scoreboard, but does something more.

Base object is the data struct that will be used across the testbench. Lets assume you are verifying a memory, then the base object would contain.

 1 #include "vera_defines.vrh"
 2 
 3 class mem_object {
 4   bit [ 7:0] addr;
 5   bit [ 7:0] data;
 6   bit rd_wr;
 7 }

Here base_object is the name of the base object, same as we have module name for each module in Verilog or entity name in VHDL. Address, data, read, write are various field of the base_object. Normally we have some default constrains and some methods(functions) which could manipulate the objects in the base object.

Transaction generator generates the transactions based on the test constrains. Normally the transaction generator applies test case constrains on the base object and generate base object based on constrain. Once generated, transaction generator passed this to driver.

A typical transaction generator would like below

  1 #include "verification_flow1.vr"
  2 
  3 class mem_txgen {
  4   mem_object mem_base;
  5   integer num_cmds;
  6   // This method generates the commands and
  7   // calls the driver
  8   task genrate_cmds() {
  9     integer i;
 10     for (i = 0 ; i < num_cmds; i++) {
 11         mem_base.addr = random();
 12 	mem_base.data = 8'h22;
 13 	mem_base.rd_wr = 0;
 14       // call the driver
 15       //driver.drive_object(mem_base);
 16     }
 17   }
 18 }

Driver drives the base object generated by the transaction generator to the DUT. To do this, it implements the DUT input protocol. Something like below.

  1 #include "verification_flow1.vr"
  2 
  3 // This connects the rtl
  4 interface top {
  5    input  clk                CLOCK;
  6    output mem_ce             PHOLD#1;
  7    output mem_rd_wr          PHOLD#1;
  8    output [7:0] mem_addr     PHOLD#1;
  9    output [7:0] mem_wr_data  PHOLD#1;
 10    input  [7:0] mem_rd_data  PSAMPLE #-1;
 11 
 12 }
 13 
 14 class mem_driver {
 15   // This method drives the DUT
 16   task drive_mem(mem_object mem_base) {
 17     @ (posedge top.clk);
 18     //Driver ce,addr,rd_wr command
 19     top.mem_ce = 1;
 20     top.mem_addr = mem_base.addr;
 21     top.mem_rd_wr = mem_base.rd_wr;
 22     if (mem_base.rd_wr == 0) {
 23       top.mem_wr_data = mem_base.data;
 24     }
 25     // Deassert all the driven signals
 26     @ (posedge top.clk);
 27     top.mem_ce= 0;
 28     top.mem_addr = 0;
 29     top.mem_rd_wr = 0;
 30     top.mem_wr_data = 0;
 31   }
 32 }

Input monitor monitors the input signals to DUT. Example in a Ethernet switch, each ingoing packet is picked by input monitor and passed to the checker.

Output monitor monitors the output signals from DUT. Example in a Ethernet switch, each outgoing packet from the switch is picked by output monitor and passed to the checker.

Checker or Scoreboards basically check if the output coming out of the DUT is correct or wrong. Basically scoreboards in e language are implemented using keyed list.

Testbench coding starts after the testbench arch document is complete, typically we start with

• base object
• transaction generator
• driver
• input monitor
• output monitor
• scoreboard

If the project is big, all the tasks can start at same time, as many engineers would be working on them.

In this phase, test execution teams executes the test cases based on the priority. Typically once the focused test cases are passing and some level of random test cases are passing, we move to regression. In regression all the test cases are run with different seeds every time there is change in RTL.

In post processing code coverage, functional coverage is checked to see if all the possible DUT functionality is covered.

Code coverage shows which part of the RTL is tested, thus is used a measurement to show how good DUT is verified. Also code coverage shows how good the functional coverage matrix is.

There are many types of code coverage as listed below.

• Line Coverage
• Branch Coverage
• Expression Coverage
• Toggle Coverage
• FSM Coverage

Line coverage or block coverage or segment coverage shows how many times each line is executed.

Branch coverage shows if all the possible branches of if..else or case statements are reached or not.

The golden of all coverage types. Expression coverage shows if all possible legal boolean values of a expression is reached or not. Generally expression coverage of 95% and above for large design is considered good.

Toggle coverage shows which bits in the RTL has toggled. Toggle coverage is used for power analysis mainly.

The FSM coverage shows, if all stats are reached, if all the possible state transition have happened.

Copyright © 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com