|
|
| |
|
|
|
|
|
| |
|
|
| |
 |
for loop
|
|
|
The for loop is the same as the for loop used in any other programming language like Verilog or Specman. |
| |
|
|
|
|
Syntax: |
| |
|
|
|
|
for (initial;condition;increment_or_decrement) statement
|
| |
|
|
|
|
- Executes an < initial assignment > once at the start of the loop.
- Executes the loop as long as an < expression > evaluates as true.
- Executes a < step assignment > at the end of each pass through the loop.
|
| |
|
|
|
|
You can specify multiple variables in the initial statement, separating them with commas. Multiple variables can also be used in the condition expression. These variables (with their initialized values) are passed to the loop and can be used within the loop for loop control |
| |
|
|
|
|
|
| |
|
|
| |
 |
Example : for loop
|
| |
|
|
|
|
1 program for_statement {
2 integer i;
3 for (i=10;i < 15; i ++ ) {
4 printf("Value of i %0d\n",i);
5 }
6 }
You could download file for_statement.vr here
|
| |
|
|
| |
|
Simulation : for loop
|
| |
|
|
|
|
Value of i 10
Value of i 11
Value of i 12
Value of i 13
Value of i 14
|
| |
|
|
| |
|
|
| |
|
|
|
|
|
| |
|
|
|
|
|
|
|
|
|
|
|
Copyright © 1998-2014 |
Deepak Kumar Tala - All rights reserved |
|
Do you have any Comment? mail me at:deepak@asic-world.com
|
|
