Vera like any other programming language supports controlling of flow of program execution. Vera supports following constructs.

• if-else
• case
• repeat
• for
• while
• foreach

We will be seeing each of this in detail in next few pages.

The if - else statement controls the execution of other statements. In programming language like Verilog, if - else controls the flow of program. When more than one statement needs to be executed for an if condition, then we need to use { and }.

Syntax:

 if (expression)
  {
    if_statement1;
    if_statement2;
    if_statementN;
  }
 else
  {
    else_statement1;
    else_statement2;
    else_statementN;
  }

  1 program if_else {
  2   integer i = 100;
  3   integer j = 10;
  4   // simple if with only one statement to execute
  5   if (i == 100)
  6     printf("value of i is 100\n");
  7   else
  8     printf("value of i is not 100\n");
  9 
 10   // if with muliple statements
 11   if (i > 60) {
 12     printf ("I is greater then 60\n");
 13     printf ("I value is %0d\n",i);
 14   } else {
 15     printf ("I is less then 60\n");
 16     printf ("I value is %0d\n",i);
 17   }
 18   // nested if 
 19   if (i > 100) {
 20     printf ("I is greater then 100\n");
 21   } else if (j > 5) {
 22     printf ("J is greater then 5\n");
 23   } else {
 24     printf ("I is not greater then 100\n");
 25     printf ("J is not greater then 5\n");
 26   }
 27 
 28 }

 value of i is 100
 I is greater then 60
 I value is 100
 J is greater then 5

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Deepak Kumar Tala - All rights reserved

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