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Virtual Port Signal Connection
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We have already seen a bit of Virtual port signal connection in data types chapter. This section describes how port signals are assigned to interface signals. Once a port signal is assigned, sampling and driving the port signal samples and drives the corresponding interface signals. |
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A port variable is a variable of a user defined virtual port, which consists of port signal members grouped together under a given user-defined port name. Port variables are handles to port instances. |
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Port variables may be initialized 3 different ways: |
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- Assigned a bind
- Assigned a new port instance
- Assigned a previously initialized port variable
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bind
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The bind construct constitutes a convenient shortcut for associating groups of port signal members with interface signals. bind is a top level construct in the Vera program that does several things. |
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- It creates an instance of a virtual port.
- It initializes the port signal members of the instance with the interface signals given in the bind.
- It defines a global port variable that references the instantiated port. This variable persists through-out the simulation.
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Syntax |
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bind virtual_port_name port_variable
{
port_signal_memberN interface_name.signal_name;
}
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Where: |
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- virtual_port_name : Is a user-defined virtual port name.
- port_variable : Must be a valid identifier.
- port_signal_member : Is a member of the user-defined virtual port.
- interface_name : Is a name of an interface declaration.
- signal_name : Is a valid Vera interface signal. You can specify subfields using signal_name[x:y].
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void bind : A subset of port signal members can be initialized, meaning you can choose to connect some or all of the signals within a bind declaration. When a port signal member is not connected, void must be used. |
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Concatenations : Within a bind, a port signal member may be initialized as a concatenation of several interface signals. |
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Creating a new port instance : Creating a new port instance requires declaring a port variable and instantiating it using the construct, port_variable = new. |
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Assigning an existing port variable : A port variable can be assigned to another port variable. The variables must be of the same user-defined port type. |
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Copying an existing port variable : A port variable can be assigned a new copy of another port variable. The variables must be of the same user-defined port type. |
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Example : bind
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1 #include "vera_defines.vrh"
2
3 // Port Declaration
4 port mem_p {
5 clock;
6 addr;
7 wr;
8 rd;
9 rdata;
10 wdata;
11 busy;
12 parity;
13 }
14
15 // This is what connects with HDL
16 interface mem_if0 {
17 input clock CLOCK;
18 output [7:0] addr PHOLD #1;
19 input [8:0] rdata PSAMPLE #-1;
20 output [7:0] wdata PHOLD #1;
21 output wr PHOLD #1;
22 output rd PHOLD #1;
23 }
24
25 interface mem_if1 {
26 input clock CLOCK;
27 output [7:0] addr PHOLD #1;
28 input [7:0] rdata PSAMPLE #-1;
29 output [7:0] wdata PHOLD #1;
30 output wr PHOLD #1;
31 output rd PHOLD #1;
32 input busy PSAMPLE #-1;
33 }
34
35
36 // Now bind interface with Port
37 bind mem_p mem_bind {
38 clock mem_if0.clock;
39 addr mem_if0.addr;
40 wr mem_if0.wr;
41 rd mem_if0.rd;
42 rdata {mem_if0.rdata[7:0],mem_if1.rdata};
43 wdata {mem_if0.wdata,mem_if1.wdata};
44 busy void;
45 parity mem_if0.rdata[8:8];
46 }
47 // Top level program
48 program virtual_port {
49 mem_p mem = mem_bind;
50 bit [15:0] data = 0;
51 integer i;
52 mem.$wr = 0;
53 mem.$rd = 0;
54 for (i=0; i < 10; i++) {
55 @ (posedge mem.$clock);
56 mem.$addr = i;
57 data = random();
58 mem.$wdata = data;
59 mem.$wr = 1;
60 printf("Writing address %0x, with data %0x\n",i,data);
61 @ (posedge mem.$clock);
62 mem.$wr = 0;
63 }
64 for (i=0; i < 10; i++) {
65 @ (posedge mem.$clock);
66 mem.$addr = i;
67 mem.$rd = 1;
68 printf("Reading address %0x",i);
69 @ (posedge mem.$clock);
70 printf(", data %0x, parity %0x\n",mem.$rdata,mem.$parity);
71 mem.$rd = 0;
72
73 }
74 }
You could download file bind_ex.vr here
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Verilog |
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1 module bind_port_verilog ();
2 // Internal variables
3 reg clk;
4 reg [7:0] mem0 [0:255];
5 reg [7:0] mem1 [0:255];
6 wire [8:0] rdata0;
7 wire [7:0] data;
8 wire [7:0] rdata1;
9
10 wire [7:0] addr;
11 wire [7:0] wdata0;
12 wire [7:0] wdata1;
13 wire wr,rd;
14
15 assign data = (rd) ? mem0[addr] : 8'b0;
16 assign rdata0 = {^data,data};
17 assign rdata1 = (rd) ? mem1[addr] : 8'b0;
18
19 always @ (addr or wr or wdata0)
20 if (wr) mem0[addr] = wdata0;
21
22 always @ (addr or wr or wdata1)
23 if (wr) mem1[addr] = wdata1;
24
25 // Connect the program here
26 virtual_port vshell(
27 .SystemClock (clk),
28 .\mem_if0.clock (clk),
29 .\mem_if0.addr (addr),
30 .\mem_if0.rdata (rdata0),
31 .\mem_if0.wdata (wdata0),
32 .\mem_if0.wr (wr),
33 .\mem_if0.rd (rd),
34 .\mem_if1.clock (clk),
35 .\mem_if1.addr (),
36 .\mem_if1.rdata (rdata1),
37 .\mem_if1.wdata (wdata1),
38 .\mem_if1.wr (),
39 .\mem_if1.rd ()
40 );
41 // Init all the variables
42 initial begin
43 clk = 0;
44 end
45 // Clock generator
46 always #1 clk = ~clk;
47
48 endmodule
You could download file bind_port.v here
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Simulation Log : bind
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Writing address 0, with data a2ac
Writing address 1, with data 581d
Writing address 2, with data adbf
Writing address 3, with data b2c9
Writing address 4, with data 165d
Writing address 5, with data 726a
Writing address 6, with data 9d46
Writing address 7, with data 9443
Writing address 8, with data 1f5f
Writing address 9, with data 8015
Reading address 0, data a2ac, parity 1
Reading address 1, data 581d, parity 1
Reading address 2, data adbf, parity 1
Reading address 3, data b2c9, parity 0
Reading address 4, data 165d, parity 1
Reading address 5, data 726a, parity 0
Reading address 6, data 9d46, parity 1
Reading address 7, data 9443, parity 1
Reading address 8, data 1f5f, parity 1
Reading address 9, data 8015, parity 1
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