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Introduction
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Like Verilog, VHDL and Specman, Vera also supports all the standard data types and also some advance data types as shown below. |
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- integer
- register
- string
- event
- Enumerated Types
- Virtual Ports
- Arrays
- Smart Queues
- Class
- Coverage Group
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We will be looking this in detail in next few pages with examples. |
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Integer
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Integers are signed variables. The upper limit for integer sizes is dependent on the host machine On 32 bit machines, the allowed |
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range is between -2,147,483,648 (32'h8000_0000) through 0 to 2,147,483,647 (32'h7FFF_FFFF). An integer may become X (unknown) when it is not initialized or when an undefined value is stored. |
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Syntax integer variable_name [=initial_value]; variable_name |
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Must be a valid identifier. initial_value Specifies the initial value for the declared variable. If this specification is omitted, the initial value of the declared variable is x (unknown). |
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Example : Integer
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1 program integer_t {
2 // Declare
3 integer i;
4 // Declare and init value
5 integer j = 0;
6 // Declare multiple and assign
7 integer m,n,o,p = 100;
8 // Print all the values
9 printf("value of i %d\n",i);
10 printf("value of j %d\n",j);
11 printf("value of m %d\n",m);
12 printf("value of n %d\n",n);
13 printf("value of o %d\n",o);
14 printf("value of p %d\n",p);
15
16 }
You could download file integer_t.vr here
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Simulation : Integer
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value of i x
value of j 0
value of m x
value of n x
value of o x
value of p 100
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Copyright © 1998-2014 |
Deepak Kumar Tala - All rights reserved |
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Do you have any Comment? mail me at:deepak@asic-world.com
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