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  ../images/main/bulllet_4dots_orange.gif state all

A special case of a state bin definition uses the all specification:

   

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state state_bin_name (all);

   

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This statement indicates that Vera creates a bin for each sampled value of the coverage point (or increments the bin hit count).

   

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Used for debugging purpose only

   

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  ../images/main/bullet_star_pink.gif Example
   

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  1 class coverage_state {
  2   bit [3:0] value;
  3   event     now;
  4 
  5   coverage_group something {
  6      sample_event = sync(ALL,now);
  7      sample value {
  8        state AB_0 (0:7);
  9        state AB_1 (4'b1000);
 10        // Used for debugging purpose only
 11        state AB_2 (all);
 12      }
 13   }
 14 
 15   task update_coverage (bit [3:0] value) {
 16      this.value = value;
 17      trigger(now);
 18   }
 19 }
 20 
 21 
 22 
 23 program test {
 24   coverage_state cov = new();
 25   bit [3:0] v; 
 26   repeat (10) {
 27     v = random();
 28     printf("Value is %d\n",v);
 29     cov.update_coverage(v);
 30     delay(1);
 31   }
 32 }    
You could download file coverage_state_all.vr here
   

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  ../images/main/bullet_star_pink.gif Simulation log
   

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 Value is 12
 Value is 13
 Value is 15
 Value is  9
 Value is 13
 Value is 10
 Value is  6
 Value is  3
 Value is 15
 Value is  5
   

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  ../images/main/bullet_star_pink.gif Coverage Report
   

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 Group : test::coverage_state::something
 
 ====================================================
 Group : test::coverage_state::something
 ====================================================
 Score   Weight  Goal    
  50.00  1       100     
 
 
 
 
 ====================================================
 
 Samples for Group : test::coverage_state::something
 
 
 
 Variable Expected Covered Percent Goal Weight 
                                               
 Total    2        1       50.00               
                                               
 value    2        1       50.00   100  1      
                                               
 
 
 ====================================================
 
 Summary for variable value
 
 
                   Expected Covered Percent 
                                            
 User Defined Bins 2        1       50.00   
                                            
 
 
 User Defined Bins for value
 
 
 Uncovered bins
 
 name count at least  
                     
 AB_1 0     1        
                     
 
 
 Excluded/Illegal bins
 
 name   count           
                       
 AB_2_5 1     excluded 
                       
 AB_2_a 1     excluded 
                       
 AB_2_f 2     excluded 
                       
 AB_2_d 2     excluded 
                       
 AB_2_3 1     excluded 
                       
 AB_2_6 1     excluded 
                       
 AB_2_9 1     excluded 
                       
 AB_2_c 1     excluded 
                       
 
 
 Covered bins
 
 name count at least  
                     
 AB_0 3     1        
                     
 
 
   

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Copyright © 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com