Illegal transition definitions associate an illegal transition with a coverage point. You define illegal transitions inside the sample construct of a coverage group.

The syntax is:

bad_trans trans_bin_name (transition_sequence_list) conditional;

The not trans modifier applies only to single transitions between two values or two value range sets. It does not apply to larger transition sequences. So, if you define a bad transaction using not trans, make sure all valid single transitions are covered in one of the transition bins. To specify multiple bad transitions, use the m_bad_trans declaration.

The syntax is:

m_bad_trans error_bin_name (exp1:exp2 -> exp3:exp4);

When you use an m_bad_trans declaration, Vera creates a bin for each transition. If you don’t specify a bin name, Vera uses the same naming conventions used for m_trans.

  1 class coverage_m_tran {
  2   bit [3:0] value;
  3   event     now;
  4 
  5   coverage_group something {
  6      sample_event = sync(ALL,now);
  7      sample value {
  8       m_trans(2:5->6:9);
  9       m_bad_trans(0:15->2:5);
 10      }
 11   }
 12 
 13   task update_coverage (bit [3:0] value) {
 14      this.value = value;
 15      trigger(now);
 16   }
 17 }
 18 
 19 
 20 
 21 program test {
 22   coverage_m_tran cov = new();
 23   bit [3:0] v; 
 24   repeat (10) {
 25     v = urandom__range(14,0);
 26     printf("Value is %d\n",v);
 27     cov.update_coverage(v);
 28     delay(1);
 29   }
 30 }    

 Value is 13
 Value is 14
 Value is  4
 VERIFICATION ERROR (VERA FUNCTIONAL COVERAGE): 
 Illegal Transition  coverage_m_tran::something:
 cov.value.t_s_0_15_s_2_5 = e->4 (coverage_m_bad_tran.vr, line 7)

 Group : test::coverage_m_tran::something
 
 ====================================================
 Group : test::coverage_m_tran::something
 ====================================================
 Score   Weight  Goal    
   0.00  1       100     
 
 
 
 
 ====================================================
 
 Samples for Group : test::coverage_m_tran::something
 
 
 
 Variable Expected Covered Percent Goal Weight 
                                               
 Total    16       0       0.00                
                                               
 value    16       0       0.00    100  1      
                                               
 
 
 ====================================================
 
 Summary for variable value
 
 
                   Expected Covered Percent 
                                            
 User Defined Bins 16       0       0.00    
                                            
 
 
 User Defined Bins for value
 
 
 Uncovered bins
 
 name               count at least  
                                   
 t_s_2_5_s_6_9:2->6 0     1        
                                   
 t_s_2_5_s_6_9:3->6 0     1        
                                   
 t_s_2_5_s_6_9:4->6 0     1        
                                   
 t_s_2_5_s_6_9:5->6 0     1        
                                   
 t_s_2_5_s_6_9:2->7 0     1        
                                   
 t_s_2_5_s_6_9:3->7 0     1        
                                   
 t_s_2_5_s_6_9:4->7 0     1        
                                   
 t_s_2_5_s_6_9:5->7 0     1        
                                   
 t_s_2_5_s_6_9:2->8 0     1        
                                   
 t_s_2_5_s_6_9:3->8 0     1        
                                   
 t_s_2_5_s_6_9:4->8 0     1        
                                   
 t_s_2_5_s_6_9:5->8 0     1        
                                   
 t_s_2_5_s_6_9:2->9 0     1        
                                   
 t_s_2_5_s_6_9:3->9 0     1        
                                   
 t_s_2_5_s_6_9:4->9 0     1        
                                   
 t_s_2_5_s_6_9:5->9 0     1        
                                   
 
 
 Excluded/Illegal bins
 
 name           count          
                              
 t_s_0_15_s_2_5 1     illegal 
                              
 
 
 

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Deepak Kumar Tala - All rights reserved

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