tran is declared inside the coverage group, and it is used for defining user defined transition bins.

Lets assume you have 4 bit sample variable and you want are interested in transitions like 0 to 1, 1 to 2, This can be done with help with tran coverage.

Another example would be, lets assume you have memory controller, and you want to know if read happened after write, Something like write->read, you can code it using transition coverage.

Transition coverage is most powerful feature, which provides means to define complex functional coverage.

  1 class coverage_tran {
  2   bit [3:0] value;
  3   event     now;
  4 
  5   coverage_group something {
  6      sample_event = sync(ALL,now);
  7      sample value {
  8       trans (2->5);
  9       trans (6->2);
 10      }
 11   }
 12 
 13   task update_coverage (bit [3:0] value) {
 14      this.value = value;
 15      trigger(now);
 16   }
 17 }
 18 
 19 
 20 
 21 program test {
 22   coverage_tran cov = new();
 23   bit [3:0] v; 
 24   repeat (10) {
 25     v = urandom__range(14,0);
 26     printf("Value is %d\n",v);
 27     cov.update_coverage(v);
 28     delay(1);
 29   }
 30 }    

 Value is 13
 Value is 14
 Value is  4
 Value is  4
 Value is  2
 Value is  8
 Value is  6
 Value is  7
 Value is  6
 Value is  2

 Group : test::coverage_tran::something
 
 ====================================================
 Group : test::coverage_tran::something
 ====================================================
 Score   Weight  Goal    
  50.00  1       100     
 
 
 
 
 ====================================================
 
 Samples for Group : test::coverage_tran::something
 
 
 
 Variable Expected Covered Percent Goal Weight 
                                               
 Total    2        1       50.00               
                                               
 value    2        1       50.00   100  1      
                                               
 
 
 ====================================================
 
 Summary for variable value
 
 
                   Expected Covered Percent 
                                            
 User Defined Bins 2        1       50.00   
                                            
 
 
 User Defined Bins for value
 
 
 Uncovered bins
 
 name      count at least  
                          
 t_s_2_s_5 0     1        
                          
 
 
 Covered bins
 
 name      count at least  
                          
 t_s_6_s_2 1     1        
                          
 
 

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Deepak Kumar Tala - All rights reserved

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