SystemVerilog supports singular value sets and set membership operators.

The syntax for the set membership operator is:

inside_expression ::= expression inside { open_range_list }

The expression on the left-hand side of the inside operator is any singular expression. The set-membership open_range_list on the right-hand side of the inside operator is a comma-separated list of expressions or ranges. If an expression in the list is an aggregate array, its elements are traversed by descending into the array until reaching a singular value. The members of the set are scanned until a match is found and the operation returns 1'b1. Values can be repeated, so values and value ranges can overlap. The order of evaluation of the expressions and ranges is non-deterministic.

The inside operator uses the equality ( == ) operator on nonintegral expressions to perform the comparison. If no match is found, the inside operator returns 1'b0. Integral expressions use the wildcard equality (==?) operator so that an x or z bit in a value in the set is treated as a do-not-care in that bit position. As with wildcard equality, an x or z in the expression on the left-hand side of the inside operator is not

treated as a do-not-care.

Note : Set membership's good use is with constraints.

  1 module set_member();
  2 
  3 int array [$] = {1,2,3,4,5,6,7};
  4 int check = 0;
  5 
  6 initial begin 
  7   if (check inside {array}) begin
  8     $display("check is inside array");
  9   end else begin
 10     $display("check is not inside array");
 11   end
 12   check = 5;
 13   if (check inside {array}) begin
 14     $display("check is inside array");
 15   end else begin
 16     $display("check is not inside array");
 17   end
 18   check = 1;
 19   // Constant range
 20   if (check inside {[0:10]}) begin
 21     $display("check is inside array");
 22   end else begin
 23     $display("check is not inside array");
 24   end
 25 
 26 end
 27 
 28 endmodule

 check is not inside array
 check is inside array
 check is inside array

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