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Coverage Points
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A covergroup can contain one or more coverage points. A coverage point can be an integral variable or an integral expression. Each coverage point includes a set of bins associated with its sampled values or its value transitions. The bins can be explicitly defined by the user or automatically created by SystemVerilog. A coverage point creates a hierarchical scope and can be optionally labeled. If the label is specified, then it designates the name of the coverage point. This name can be used to add this coverage point to a cross coverage specification or to access the methods of the coverage point. If the label is omitted and the coverage point is associated with a single variable, then the variable name becomes the name of the coverage point. Otherwise, an implementation can generate a name for the coverage point only for the purposes of coverage reporting, that is, generated names cannot be used within the language. |
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Coverage point can contain optional iff statement to disable the coverage collection, when condition is active, say reset is asserted and we don't want to collect coverage during reset. |
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A coverage point bin associates a name and a count with a set of values or a sequence of value transitions. If the bin designates a set of values, the count is incremented every time the coverage point matches one of the values in the set. If the bin designates a sequence of value transitions, the count is incremented every time the coverage point matches the entire sequence of value transitions. |
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The bins for a coverage point can be automatically created by SystemVerilog or explicitly defined using the bins construct to name each bin. If the bins are not explicitly defined, they are automatically created by SystemVerilog. The number of automatically created bins can be controlled using the auto_bin_max coverage option. |
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The bins construct allows creating a separate bin for each value in the given range list or a single bin for the entire range of values. To create a separate bin for each value (an array of bins), the square brackets, [], must follow the bin name. To create a fixed number of bins for a set of values, a number can be specified inside the square brackets. The open_range_list used to specify the set of values associated with a bin shall be constant expressions, instance constants (for classes only), or non-ref arguments to the coverage group. It shall be legal to use the $ primary in an open_value_range of the form [ expression : $ ] or [ $ : expression ]. |
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If a fixed number of bins is specified and that number is smaller than the specified number of values, then the possible bin values are uniformly distributed among the specified bins. |
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The expression within the iff construct at the end of a bin definition provides a per-bin guard condition. If the expression is false at a sampling point, the count for the bin is not incremented. |
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The default specification defines a bin that is associated with none of the defined value bins. The default bin catches the values of the coverage point that do not lie within any of the defined bins. However, the coverage calculation for a coverage point shall not take into account the coverage captured by the default bin. The default bin is also excluded from cross coverage The default sequence form can be used to catch all transitions (or sequences) that do not lie within any of the defined transition bins. The default sequence specification does not accept multiple transition bins (i.e., the [] notation is not allowed). |
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We will be covering following next few pages |
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- Generic coverage group
- Implicit bins creation
- Explicity bins creation
- Array of bins creation
- Default bins creation
- Transition bins creation
- Single value transition
- Sequence of transition
- Set of transition
- Consecutive repetion
- Range of repetition
- Goto repetition
- Non consecutive repetition
- Wildcard bin creation
- Ignore bin creation
- Illegal bin creation
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Basic example
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1 //+++++++++++++++++++++++++++++++++++++++++++++++++
2 // Define the interface with coverage
3 //+++++++++++++++++++++++++++++++++++++++++++++++++
4 interface mem_if (input wire clk);
5 logic reset;
6 logic we;
7 logic ce;
8 logic [7:0] datai;
9 logic [7:0] datao;
10 logic [7:0] addr;
11 //=================================================
12 // Clocking block for testbench
13 //=================================================
14 clocking cb @ (posedge clk);
15 output reset, we, ce, datai,addr;
16 input datao;
17 endclocking
18 //=================================================
19 // Coverage Group in interface
20 //=================================================
21 covergroup memory @ (posedge ce);
22 address : coverpoint addr {
23 bins low = {0,50};
24 bins med = {51,150};
25 bins high = {151,255};
26 }
27 data_in : coverpoint datai {
28 bins low = {0,50};
29 bins med = {51,150};
30 bins high = {151,255};
31 }
32 data_out : coverpoint datao {
33 bins low = {0,50};
34 bins med = {51,150};
35 bins high = {151,255};
36 }
37 read_write : coverpoint we {
38 bins read = {0};
39 bins write = {1};
40 }
41 endgroup
42 //=================================================
43 // Instance of covergroup
44 //=================================================
45 memory mem = new();
46
47 endinterface
48 //+++++++++++++++++++++++++++++++++++++++++++++++++
49 // DUT With interface
50 //+++++++++++++++++++++++++++++++++++++++++++++++++
51 module simple_if (mem_if mif);
52 // Memory array
53 logic [7:0] mem [0:255];
54
55 //=================================================
56 // Read logic
57 //=================================================
58 always @ (posedge mif.clk)
59 if (mif.reset) mif.datao <= 0;
60 else if (mif.ce && ! mif.we) mif.datao <= mem[mif.addr];
61
62 //=================================================
63 // Write Logic
64 //=================================================
65 always @ (posedge mif.clk)
66 if (mif.ce && mif.we) mem[mif.addr] <= mif.datai;
67
68 endmodule
69
70 //+++++++++++++++++++++++++++++++++++++++++++++++++
71 // Testbench
72 //+++++++++++++++++++++++++++++++++++++++++++++++++
73 module coverage_covergroup();
74
75 logic clk = 0;
76 always #10 clk++;
77 //=================================================
78 // Instianciate Interface and DUT
79 //=================================================
80 mem_if miff(clk);
81 simple_if U_dut(miff);
82 //=================================================
83 // Default clocking
84 //=================================================
85 default clocking dclk @ (posedge clk);
86
87 endclocking
88 //=================================================
89 // Test Vector generation
90 //=================================================
91 initial begin
92 miff.reset <= 1;
93 miff.ce <= 1'b0;
94 miff.we <= 1'b0;
95 miff.addr <= 0;
96 miff.datai <= 0;
97 ##1 miff.reset <= 0;
98 for (int i = 0; i < 3; i ++ ) begin
99 ##1 miff.ce <= 1'b1;
100 miff.we <= 1'b1;
101 miff.addr <= i;
102 miff.datai <= $random;
103 ##3 miff.ce <= 1'b0;
104 $display ("@%0dns Write access address %x, data %x",
105 $time,miff.addr,miff.datai);
106 end
107 for (int i = 0; i < 3; i ++ ) begin
108 ##1 miff.ce <= 1'b1;
109 miff.we <= 1'b0;
110 miff.addr <= i;
111 ##3 miff.ce <= 1'b0;
112 $display ("@%0dns Read access address %x, data %x",
113 $time,miff.addr,miff.datao);
114 end
115 #10 $finish;
116 end
117
118 endmodule
You could download file coverage_points.sv here
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Simulation : Basic example
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@90ns Write access address 00, data 24
@170ns Write access address 01, data 81
@250ns Write access address 02, data 09
@330ns Read access address 00, data 24
@410ns Read access address 01, data 81
@490ns Read access address 02, data 09
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Report : Basic example
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@90ns Write access address 00, data 24
@170ns Write access address 01, data 81
@250ns Write access address 02, data 09
@330ns Read access address 00, data 24
@410ns Read access address 01, data 81
@490ns Read access address 02, data 09
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