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Transition bins creation : Consecutive repetion
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Sometime it is required to check if same values repeated N number of time. This can be done by manually typing the value N times as in below. |
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WRITE=>WRITE=>WRITE=>WRITE |
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It works, but the problem is if you have to measure long sequence, then it is time waste. Systemverilog provides syntax to do it. |
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4[*WRITE] |
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Example : Consecutive repetions creation
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1 module test();
2
3 logic [2:0] addr;
4 reg ce;
5
6 covergroup address_cov () @ (posedge ce);
7 ADDRESS : coverpoint addr {
8 bins adr_0_2times = (0[*2]);
9 bins adr_1_3times = (1[*3]);
10 bins adr_2_4times = (2[*4]);
11 }
12 endgroup
13
14 address_cov my_cov = new();
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16 initial begin
17 ce <= 0;
18 addr <= 2;
19 $monitor("ce %b addr 8'h%x",ce,addr);
20 repeat (10) begin
21 ce <= 1;
22 #10 ;
23 ce <= 0;
24 #10 ;
25 end
26 end
27
28 endmodule
You could download file cons_repetion_bin.sv here
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Simulation : Consecutive repetions creation
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ce 1 addr 8'h2
ce 0 addr 8'h2
ce 1 addr 8'h2
ce 0 addr 8'h2
ce 1 addr 8'h2
ce 0 addr 8'h2
ce 1 addr 8'h2
ce 0 addr 8'h2
ce 1 addr 8'h2
ce 0 addr 8'h2
ce 1 addr 8'h2
ce 0 addr 8'h2
ce 1 addr 8'h2
ce 0 addr 8'h2
ce 1 addr 8'h2
ce 0 addr 8'h2
ce 1 addr 8'h2
ce 0 addr 8'h2
ce 1 addr 8'h2
ce 0 addr 8'h2
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Report : Consecutive repetions creation
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===========================================================
Group : test::address_cov
===========================================================
SCORE WEIGHT GOAL
33.33 1 100
-----------------------------------------------------------
Summary for Group test::address_cov
CATEGORY EXPECTED UNCOVERED COVERED PERCENT
Variables 3 2 1 33.33
Variables for Group test::address_cov
VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT
ADDRESS 3 2 1 33.33 100 1
-----------------------------------------------------------
Summary for Variable ADDRESS
CATEGORY EXPECTED UNCOVERED COVERED PERCENT
User Defined Bins 3 2 1 33.33
User Defined Bins for ADDRESS
Uncovered bins
NAME COUNT AT LEAST NUMBER
adr_1_3times 0 1 1
adr_0_2times 0 1 1
Covered bins
NAME COUNT AT LEAST
adr_2_4times 7 1
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Copyright © 1998-2014 |
Deepak Kumar Tala - All rights reserved |
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Do you have any Comment? mail me at:deepak@asic-world.com
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