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Resolved Logic Vectors
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In real hardware, there are times when we need to model tristate bus. So that multiple agents can drive same bus. Like PCI bus or Microprocessor 8085 address and data bus. |
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To help with this SystemC provides Resovled Logic Vectors. In this agent which is driving 0, 1 win's the bus. In the below image, we have Module A driving 1 and Module B driving Z. Resolve signal Y gets 1. |
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When Module A drives 1 and Module B drives 0, then output Y is X. X denotes Unknown value. |
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Resolve of Logic Values
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0
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1
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Z
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X
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0
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0
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X
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0
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X
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1
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X
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1
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1
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X
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Z
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0
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1
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Z
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X
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X
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X
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X
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X
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X
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Example : Resolved Logic Vectors
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1 #include <systemc.h>
2
3 SC_MODULE(module_A) {
4 sc_in_rv<1> in;
5 sc_out_rv<1> out;
6 sc_inout_rv<4> inout;
7
8 void body () {
9 out.write(in);
10 if (in.read() == 1) {
11 out.write(1);
12 inout.write(rand());
13 } else {
14 out.write('z');
15 inout.write('zzzz');
16 }
17 }
18
19 SC_CTOR(module_A) {
20 SC_METHOD(body);
21 sensitive << in;
22 }
23 };
You could download file resolve.cpp here
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Copyright © 1998-2025 |
Deepak Kumar Tala - All rights reserved |
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Do you have any Comment? mail me at:deepak@asic-world.com
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