1 //-----------------------------------------------------
  2 // Design Name : half_adder_gates
  3 // File Name   : half_adder_gates.v
  4 // Function    : CCITT Serial CRC
  5 // Coder       : Deepak Kumar Tala
  6 //-----------------------------------------------------
  7 module half_adder_gates(x,y,sum,carry);
  8 input x,y;
  9 output sum,carry;
 10 
 11 and U_carry (carry,x,y);
 12 xor U_sum (sum,x,y);
 13 
 14 endmodule

  1 //-----------------------------------------------------
  2 // Design Name : full_adder_gates
  3 // File Name   : full_adder_gates.v
  4 // Function    : Full Adder Using Gates
  5 // Coder       : Deepak Kumar Tala
  6 //-----------------------------------------------------
  7 module full_adder_gates(x,y,z,sum,carry);
  8 input x,y,z;
  9 output sum,carry;
 10 wire and1,and2,and3,sum1;
 11 
 12 and U_and1 (and1,x,y),
 13     U_and2 (and2,x,z),
 14     U_and3 (and3,y,z);
 15 or  U_or   (carry,and1,and2,and3);
 16 xor U_sum (sum,x,y,z);
 17 
 18 endmodule

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