1 module memory(
  2 address,
  3 data_in,
  4 data_out,
  5 read_write,
  6 chip_en
  7 );
  8 
  9 input [7:0] address, data_in;
 10 output [7:0] data_out;
 11 input read_write, chip_en;
 12 
 13 reg [7:0] mem [0:255];
 14 
 15 always @ (address or data_in or read_write or chip_en)
 16 if (read_write == 1 && chip_en == 1) begin
 17   mem[address] = data_in;
 18 end
 19 
 20 assign data_out = (read_write == 0 && chip_en == 1) ? mem[address] : 0;
 21 
 22 endmodule

  1 `include "memory.v"
  2 module memory_tb();
  3 
  4 wire [7:0] address, data_in;
  5 wire [7:0] data_out;
  6 wire  read_write, chip_en;
  7 reg clk;
  8 
  9 // Connect the program here
 10 memory_top vshell(
 11  .SystemClock (clk),
 12  .\mem_if.clock       (clk),
 13  .\mem_if.address     (address),
 14  .\mem_if.data_in     (data_in),
 15  .\mem_if.data_out    (data_out),
 16  .\mem_if.chip_en     (chip_en),
 17  .\mem_if.read_write  (read_write)
 18 );
 19 
 20 
 21 initial begin
 22   clk = 0;
 23 end	
 24 
 25 always  #1  clk = ~clk;
 26 
 27 memory U_memory(
 28 .address             (address),
 29 .data_in             (data_in),
 30 .data_out            (data_out),
 31 .read_write          (read_write),
 32 .chip_en             (chip_en)
 33 );
 34 endmodule

  1 #include "mem_base_object.vrh"
  2 #include "mem_ports.vrh"
  3 #include "mem_if.vrh"
  4 #include "mem_binds.vrh"
  5 #include "mem_driver.vr"
  6 #include "mem_txgen.vr"
  7 #include "mem_scoreboard.vr"
  8 #include "mem_ip_monitor.vr"
  9 #include "mem_op_monitor.vr"
 10 
 11 
 12 program memory_top {
 13   mem_txgen txgen;
 14   mem_ports ports;
 15   mem_scoreboard sb;
 16   mem_ip_monitor ipm;
 17   mem_op_monitor opm;
 18 
 19   ports = mem_p;
 20   sb    = new();
 21   ipm   = new (sb, ports);
 22   opm   = new (sb, ports);
 23   txgen = new(ports);
 24 
 25   txgen.gen_cmds();
 26 
 27   repeat (20) @ (posedge CLOCK);
 28 
 29 }

Copyright © 1998-2014

Deepak Kumar Tala - All rights reserved

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