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Verification Of UART
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In this example, we verify a simple UART. |
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This testbench will slightly different from what we have seen till now. |
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So the verification components are split into following blocks |
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- TX generator
- RX generator
- TX monitor
- RX monitor
- Scoreboard
- SystemVerilog testbench top
- SystemVerilog Ports file
- HDL Testbench top
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We are going to have some more components that like reset. Logic to control when to terminate. |
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Copyright © 1998-2025 |
Deepak Kumar Tala - All rights reserved |
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Do you have any Comment? mail me at:deepak@asic-world.com
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