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D Flip-Flop
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Asynchronous reset D- FF
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1 //-----------------------------------------------------
2 // Design Name : dff_async_reset
3 // File Name : dff_async_reset.sv
4 // Function : D flip-flop async reset
5 // Coder : Deepak Kumar Tala
6 //-----------------------------------------------------
7 module dff_async_reset (
8 input wire data , // Data Input
9 input wire clk , // Clock Input
10 input wire reset , // Reset input
11 output reg q // Q output
12 );
13 //-------------Code Starts Here---------
14 always_ff @ ( posedge clk iff reset == 1 or negedge reset)
15 if (~reset) begin
16 q <= 1'b0;
17 end else begin
18 q <= data;
19 end
20
21 endmodule //End Of Module dff_async_reset
You could download file sv_examples here
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Synchronous reset D- FF
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1 //-----------------------------------------------------
2 // Design Name : dff_sync_reset
3 // File Name : dff_sync_reset.sv
4 // Function : D flip-flop sync reset
5 // Coder : Deepak Kumar Tala
6 //-----------------------------------------------------
7 module dff_sync_reset (
8 input wire data , // Data Input
9 input wire clk , // Clock Input
10 input wire reset , // Reset input
11 output reg q // Q output
12 );
13 //-------------Code Starts Here---------
14 always_ff @ ( posedge clk)
15 if (~reset) begin
16 q <= 1'b0;
17 end else begin
18 q <= data;
19 end
20
21 endmodule //End Of Module dff_sync_reset
You could download file sv_examples here
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Copyright © 1998-2025 |
Deepak Kumar Tala - All rights reserved |
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Do you have any Comment? mail me at:deepak@asic-world.com
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